Memory devices find ubiquitous use in computing devices. Dynamic random access memory (DRAM) is commonly used as working memory in computing devices. The working memory is often volatile (it loses state if power is interrupted to the system), and provides temporary storage for data and programs (code) to be accessed and executed by the system processor(s).
There are multiple types and variations of DRAM (one example being synchronous DRAM (SDRAM)). Being dynamic, DRAM requires continuous or regular refreshing of the data bits stored in the memory device. The refreshing is generally controlled by a memory controller, which periodically accesses the data bits in the memory device. DRAMs typically also have a self-refresh mode, which reduces power consumption by the memory device. In self-refresh, all internal clocks are typically turned off within the memory device, as well as input channels except CKE (clock enable), which is traditionally a unidirectional signal used by the memory controller to trigger self-refresh.
Although the memory controller triggers self-refresh with the CKE, self-refresh is typically controlled internally to the memory device, which means the memory controller does not have visibility into when the self-refresh actually begins and ends. As a result, if the memory controller access the memory device and gets no response, the memory controller must traditionally assume the memory device is in self-refresh and wait for the refresh cycle time (tRFC) plus an additional guard band time (e.g., 10 ns) before sending a command. For a 4 Gbit device, tRFC is expected to be in the range of 300 ns; but tRFC approximately doubles for doubling of device density. Thus, the delay for the memory controller to send a command continues to increase, and may produce less desirable performance.
FIG. 1 is a timing diagram of an embodiment of a prior art system with a self-refresh mode. Diagram 100 represents various signals present in known systems. Diagram 100 represents signals within a memory device, and specifically a memory device with a self-refresh mode. The clock signal (CK) is illustrated with various timing points (T0, T1, T2, . . . ) illustrated at the rising edge of the clock. Clock enable (CKE) is a unidirectional signal triggered by a memory controller to direct the memory device to enter self-refresh. The entering and exiting of self-refresh is controlled by the memory device itself; thus, actual timing of when and how long the memory device enters into self-refresh is not visible to the memory controller.
As shown, the command signal (CMD) illustrates a nop (no operation) at T0, and assumes that a self-refresh enable (SRE) command is issued at approximately T1. Another nop is issued, and the memory device enters self-refresh within a self-refresh enable clock count (tCKSRE). The memory device takes the memory device out of self-refresh prior to a delay that would cause a risk of loss of data within the memory. The amount of time for the self-refresh exit (SRX) command to be generated is within the self-refresh exit clock count (tCKSRX). The timing of SRX may coincide closely with the memory controller re-enabling the clock by switching CKE.
The first command after SRX (Tc1) is a nop (Td0). After a period of time tXS (shown at Te0), a valid command can be issued, if the command does not require a locked DLL. The value of tXS is (tRFC+guard band). The first valid command that can be issued after self-refresh exit is after a period of time tXSDLL (shown at Tf0). It will be understood from the time breaks, as well as in general that diagram 100 is not necessarily shown to scale.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.